An etchant that etches WSi selectively with respect to InAlAs or InGaAs, i.e., an etchant that etches WSi at a very high etching rate and etches InAlAs or InGaAs at a very low etching rate, has not been discovered so far. Therefore, RIE (reactive ion etching) or the like has been employed when a WSi layer on an InGaAs or InAlAs layer is etched selectively with respect to the InGaAs or InAlAs layer.
FIGS. 9(a)-9(d) are cross-sectional views illustrating process steps in a conventional method of fabricating a MESFET. In these figures, reference numeral 1 designates a semi-insulating InP substrate, numeral 2 designates an undoped InP buffer layer, numeral 3 designates an n type active layer comprising Si-doped InAlAs or InGaAs, numeral 4 designates a WSi layer, numerals 4a and 4b designate a source electrode and a drain electrode both comprising WSi, respectively, numeral 5 designates a gate electrode comprising Ti/Al, and numerals 6a and 6b designate a first photoresist and a second photoresist, respectively.
A description is given of the fabrication process.
Initially, as illustrated in FIG. 9(a), a buffer layer 2 and an n type active layer 3 are grown on an InP substrate 1 by MBE (molecular beam epitaxy) or MOCVD (metal organic chemical vapor deposition), and a WSi layer 4 is deposited on the n type active layer 3 by sputtering.
In the step of FIG. 9(b), a first photoresist 6a is formed on the WSi layer 4 and patterned by conventional photolithographic techniques to form an opening opposite a region where a gate electrode is later fabricated. Using the photoresist 6a as a mask, a portion of the WSi layer 4 which is exposed in the opening of the photoresist 6a is etched and removed selectively with respect to the n type active layer 3 by RIE. Preferably, a fluorine-based gas mixture, such as SF.sub.6 and CHF.sub.3, is used in the RIE process. As a result of the RIE, a source electrode 4a and a drain electrode 4b are produced.
After removal of the photoresist 6a, as illustrated in FIG. 9(c), a second photoresist 6b is formed on the source and drain electrodes 4a and 4b and on the n type active layer 3, and the photoresist 6b is patterned by conventional photolithographic techniques to form an opening opposite a central region between the source electrode 4a and the drain electrode 4b. Using the photoresist 6b as a mask, a Ti/Al layer is deposited by EB (Electron Beam) deposition, and unnecessary portions of the Ti/Al layer on the photoresist 6b are removed with the photoresist 6b by the lift-off technique, producing a gate electrode 5 (FIG. 9(d)).
In the conventional process of fabricating process of a MESFET, when the spaced apart source and drain electrodes 4a and 4b are produced, a portion of the WSi layer 4 must be removed selectively with respect to the n type active layer 3 comprising Si-doped InAlAs or InGaAs. However, since an etchant that etches WSi selectively with respect to InAlAs or InGaAs has not been discovered yet, the WSi layer 4 is etched by RIE as shown in FIG. 9(b). Since the RIE process employs a fluorine-based gas mixture, such as SF.sub.6 and CHF.sub.3, fluorine adheres to the n type active layer 3 that is exposed as a result of the RIE and infiltrates into the active layer 3. In the n type active layer 3, the fluorine combines with Si that is a dopant impurity of the active layer 3, whereby the carrier concentration of the active layer 3 is reduced. As a result, the FET characteristics are degraded.
FIGS. 10(a)-10(c) are cross-sectional views illustrating process steps in a conventional method of fabricating an HEMT with a T-shaped gate electrode. In the figures, reference numeral 11 designates a semi-insulating InP substrate, numeral 12 designates an undoped InAlAs buffer layer, numeral 13 designates an undoped InGaAs active layer, and numeral 14 designates an electron supply layer. The electron supply layer 14 comprises an Si planar doped layer 14a, i.e., a layer two-dimensionally doped with Si in a concentration of 4.times.10.sup.12 cm.sup.-2, and an undoped InAlAs layer 14b having a thickness of about 300 .ANG.. Reference numeral 15 designates an n type InGaAs cap layer about 300 .ANG. thick. The cap layer 15 is doped with an n type producing impurity in a concentration of about 5.times.10.sup.18 cm.sup.-3 so that it makes an ohmic contact with a source electrode and a drain electrode disposed thereon. Reference numeral 15a designates a gate recess formed in the cap layer 15. Reference numerals 16a and 16b designate a source electrode and a drain electrode, respectively, both comprising WSi about 1000 .ANG. thick. Reference numeral 19 designates a gate electrode comprising Ti/Al. Reference numeral 17 designates an EB (electron beam) resist, and numeral 18 designates a photoresist.
A description is given of the fabrication process.
Initially, there are successively grown on an InP substrate 11, an undoped InAlAs buffer layer 12, an undoped InGaAs active layer 13, an Si planar doped layer 14a, an undoped InAlAs layer 14b, and an n type InGaAs cap layer 15. Preferably, these layers are grown by MBE (Molecular Beam Epitaxy) or MOCVD (Metal Organic Chemical Vapor Deposition). Thereafter, an EB resist 17 and a photoresist 18 are formed on the cap layer 15, and a portion of the photoresist 18 opposite a region where a gate electrode is later fabricated is removed using conventional photolithographic techniques to form an opening having a width of about 0.5 .mu.m. Further, a portion of the EB resist 17 in the center of the opening of the photoresist 18 is removed by conventional photolithographic techniques using electron beam exposure, forming an opening having a width of about 0.1 .mu.m. The opening of the photoresist 18 and the opening of the EB resist 17 form an upper case Roman letter T at the cross-section perpendicular to the surface of the substrate 11 (FIG. 10(a)).
Using the photoresist 18 and the EB resist 17 as masks, the n type InGaAs cap layer 15 exposed in the opening of the EB resist 17 is wet-etched with an inorganic acid mixture, such as H.sub.3 PO.sub.4 and H.sub.2 O.sub.2, to a gate recess 15a (FIG. 10(b)). Since the gate recess 15a is formed by the isotropic wet etching, the width of the recess 15a is larger than the width of the opening of the EB resist 17.
In the step of FIG. 10(c), using the photoresist 18 and the EB resist 17 as masks, a gate metal, such as Ti/Au, is deposited by evaporation, and unnecessary portions of the gate metal are removed with the photoresist 18 and the EB resist 17 by the lift-off technique, thereby producing a gate electrode 19 having a T shape at the cross-section perpendicular to the surface of the substrate 11.
Finally, using an upper overhanging part of the T-shaped gate electrode 19 as a mask, WSi is deposited on the cap layer 15 by EB deposition, producing a source electrode 16a and a drain electrode 16b (FIG. 10(d)).
The width of the upper overhanging part of the T-shaped gate electrode 19 is about 0.5 .mu.m, and the source electrode 16a and the drain electrode 16b are not produced beneath the overhanging part, so that the space between the source electrode 16a and the drain electrode 16b (hereinafter referred to as source to drain distance) is about 0.5 .mu.m. Although it is not shown in the figure, regions of the cap layer 15 where the source electrode 16a and the drain electrode 16b are not produced are masked with a resist or the like in advance. Further, in the step of FIG. 10(d), since a WSi layer (not shown) is deposited on the top of the T-shaped gate electrode 19, at least a part of the gate electrode 19 where bonding is later performed should be masked or the WSi layer on that part should be removed by etching or the like.
In the above-described method of fabricating an HEMT, since the source electrode 16a and the drain electrode 16b are formed by evaporation using the upper overhanging part of the T-shaped gate electrode 19 as a mask, the source to drain distance is equivalent to the width of the upper overhanging part of the T-shaped gate electrode 19, that is, the source to drain distance is restricted to the width of the upper overhanging part of the gate electrode 19. Since the source to drain distance cannot be reduced, the source resistance and the drain resistance cannot be reduced. As a result, the characteristics of the HEMT are not improved.